Wafer devices, such as MEMS devices and IC devices, may include two or more wafers that are bonded to one another. Either or both of the wafers may include micromachined and/or integrated circuit components that are formed through various processes. For convenience, one of the wafers is referred to hereinafter as the device wafer, while the other of the wafers is referred to hereinafter as the cap wafer.
It is often necessary or desirable to provide connections to components through one or both of the wafers. For example, it may be necessary or desirable to provide electrical connections through the cap wafer to electrical components on the device wafer. Therefore, holes (often referred to as “through-hole vias”) can be formed through the cap wafer in order to expose components on the device wafer. Interconnections can be formed through the through-hole vias to the components, for example, using a material deposition process, in order to allow connectivity from the top side of the cap wafer through to the components on the device wafer.
One problem with such wafer devices is that there can be gaps between the cap wafer and the device wafer when the cap wafer and the device wafer are bonded together. The gaps can be caused by the thickness of a bonding material, uneven topography of the wafer surfaces, and/or the inherent space between adjacent (unbonded) materials. The size of the gaps can be different at different locations along the surfaces of the wafers.
When there is a significant gap between the bottom of a through-hole via and a corresponding component on the device wafer, it can be difficult to form an interconnection through the through-hole via to the component. For example, in a typical material deposition process used to form interconnections (e.g., electrodes), the interconnection is “grown” by building up layers of material. Generally speaking, the material requires a surface on which to grow. Thus, the material will generally adhere to and grow on the inside surface of the through-hole via, on the surface of the component, and on the successively deposited layers of material. Depending on the size of the gap between the through-hole via and the corresponding component, it could take a great deal of time to grow the interconnection. For example, the gap between the cap wafer and the device wafer could be on the order of several microns, and it could literally take many days to grow an interconnection across such a gap using typical deposition techniques. This is expensive in terms of time and production costs.
FIGS. 1A-1C demonstrate interconnection of through-wafer vias as known in the art. FIG. 1A shows a cross-sectional view of a capped wafer device including a cap wafer 102 having pre-formed vias 104, cavity 108, and bonding materials 106 and a device wafer 110 having a MEMS device 114 (such as an optical mirror, inertial sensor, comb fingers, or other device) and bond pads 112. FIG. 1B shows the gap 116 that remains when the cap wafer 102 and the device wafer 110 are bonded to one another. FIG. 1C shows interconnections 118 that are formed through the through-hole vias 104 to the components 112 across the gap 116.